Pre-silicon quality and reliability
Design validation, sign-off methodologies, EM/IR analysis, voltage-level verification, static crosstalk analysis, and floating-gate checks.
Semiconductor engineering leader
I lead engineering teams at the intersection of circuit simulation, EDA, design automation, data engineering, and machine learning for analog and mixed-signal silicon.
About
My work spans the full path from design methodology to scalable engineering platforms. At Apple Silicon Engineering, I lead Data and MLOps engineering for simulation and designer workflows supporting SERDES, PLLs, sensors, and complex IP.
Earlier at Texas Instruments and National Semiconductor, I led development of circuit simulators, signal-integrity and reliability tools, design-validation flows, online design tools, and customer-facing EDA integrations.
Areas of expertise
Design validation, sign-off methodologies, EM/IR analysis, voltage-level verification, static crosstalk analysis, and floating-gate checks.
SPICE, Verilog-A, Verilog, compact device models, behavioral modeling, and multi-domain co-simulation.
Designer-facing flows, simulation orchestration, API-based tool integration, design collateral, and scalable automation.
Global team leadership, organization design, resource allocation, operating metrics, talent development, and cross-functional execution.
Selected experience
Lead Data and MLOps engineering for simulation platforms, data pipelines, distributed simulation, and ML-enabled designer workflows used by hundreds of analog and mixed-signal designers.
Set architecture direction for simulation, design automation, and infrastructure; led 100K+ simulation campaigns and a distributed team of 20+ engineers.
Led WEBENCH and TIspice initiatives, including tools adopted by 100K+ engineers, customer design exchange, PCB thermal design, and circuit simulation.
Developed analog and mixed-signal simulators, EM/IR and reliability analysis, signal-integrity tools, layout automation, and behavioral modeling.
Selected impact
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